A computer system's performance is in part dependent on the speed of accessing the system memory (e.g., the main general-purpose storage region of the computer system.) For example, microprocessors may only execute instructions as fast as the data operands are provided to the microprocessor. Many of the data operands need to be obtained from the system memory.
Therefore, the speed of accessing the system memory has a large impact on the speed at which a microprocessor is able to complete execution of instructions. As a result, there is a continuous need to increase the speed of accessing system memory.
Access to the system memory is commonly controlled by a unit referred to as the memory controller. The memory controller receives memory access requests (e.g., request to read data stored in memory or request to write data to memory) from other units within the computer system (e.g., the Central Processing Unit (CPU), Graphics accelerator, etc.) The memory controller arbitrates the order in which multiple requests will be granted access to memory. Moreover, the memory controller also prepares/translates memory access requests to be transferred to the system memory. For example, the memory controller may decode a memory request into one or more commands (depending upon the protocol of the memory) to be executed by the system memory in order to complete the memory request.
The rate at which the memory controller processes the memory requests is in part dependent on the bandwidth (i.e., rate of transmitting data) of the memory bus (i.e., an electronic pathway) between the memory controller and the system memory. For example, the memory controller typically may only submit requests to the system memory at a rate equal to or less than the rate of transmitting the data/controls on the memory bus. Otherwise, the memory requests will be prepared by the memory controller faster than they can be transmitted and a bottle neck effect will be the result.
In the past, the bandwidth of the memory bus has been relatively slow. As a result, memory controllers have been able to process memory request in a serial fashion (i.e., completing one memory request before beginning to process a subsequent memory request). Never the less, memory controllers were still able to fill most of the bandwidth of the memory bus, despite processing the requests in a serial fashion.
Advancements in the technology of the memory bus, however, have increased the bandwidth of transmitting data/controls on the memory bus. As a result, there is a need to increase the speed of the memory controller to process memory requests in order to take advantage of the increased bandwidth.